It can be appreciated that several trends presently exist in the electronics industry. Devices are continually getting smaller, faster and requiring less power, while simultaneously being able to support and perform a greater number of increasingly complex and sophisticated functions. One reason for these trends is an ever increasing demand for small, portable and multifunctional electronic devices such as cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market.
Accordingly, there is a continuing trend in the semiconductor industry to manufacture integrated circuits (ICs) with higher device densities by scaling down dimensions (e.g., at submicron levels) on semiconductor wafers. To accomplish such high densities, smaller feature sizes, smaller separations between features and layers, and/or more precise feature shapes are required, such as metal interconnects or leads, for example. The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication processes by providing or ‘packing’ more circuits on a semiconductor die and/or more die per semiconductor wafer, for example.
As these feature sizes and separations between the features become smaller, alignments between such features also become more demanding.
Contact alignment is critical for static random access memory (SRAM) device yield. By way of example, contact (CONT) to GATE misalignment may result in shorts, leading to single-bit fails (SBFs). CONT to ACTIVE (or MOAT) misalignment can lead to very high resistance and junction leakage, which also leads to SBFs or IDDQ (Quiescent drain current) issues. One conventional strategy to alleviate these problems has been to align the CONT layer to the GATE. However, this solution results in poor alignment with respect to the ACTIVE layer as the CONT to ACTIVE alignment will then become the RMS error of the CONT-GATE and the GATE-ACTIVE in this strategy. As a result, yield may suffer with CONT-ACTIVE misalignment, or alternately, the SRAM bitcell may need to be enlarged to provide additional margin against misalignment.
Consequently, for advanced scaling nodes such as 45 nm and beyond, it would be desirable to be able to provide improved alignment capabilities in the fabrication of SRAM devices and other such semiconductor devices.